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安永守利 論文・学会発表リスト

論文・学会発表リスト

ギャラリー

2019年3月現在 論文・学会発表リスト

1. 論文誌(査読有り)に掲載された筆頭執筆論文(21件)

[1] M.Yasunaga, Y.Funatsu, S.Kojima, K.Otsuka and T.Suzuki, “Ultrasonic Velocity Near The Martenstic Transformation Temperature,” Journal de Physique, Vol.43, No.12, pp.C4 603-608, December 1982.

[2] M.Yasunaga, Y.Funatsu, S.Kojima, K.Otsuka and T.Suzuki, “Measurement of Elastic Constants,” Scripta METALLURGICA, Vol.17, pp.1091-1094, 1983.

[3] 安永守利, 浅井光男, 柴田克成, 山田稔, “ニューラルネットワーク集積回路の自律的な欠陥救済能力,” 電子情報通信学会論文誌, Vol.J75-D-I, No.11, pp.1099-1108, November 1992.

[4] Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Katsunari Shibata, Mitsuo Ooyama, Minoru Yamada, Takahiro Sakaguchi, Masashi Hashimoto, “A Self-Learning Digital Neural Network Using Wafer-Scale LSI,” IEEE Journal of Solid-State Circuits, Vol.28, No.2, pp.106-114, February 1993.

[5] Moritoshi Yasunaga and Hiroaki Kitano, “Robustness of the Memory-Based Reasoning Implemented by Wafer Scale Integration,” IEICE Transaction on Information and Systems, Vol.E76-D, No.3, pp.336-344, March 1993.

[6] 安永守利, “ウェーハスケール集積回路による遺伝的アルゴリズムのハードウェア化 ―WSIのLDA (Leaving Defects Alone) アプローチ―,” 電子情報通信学会論文誌,Vol.J77-D-I, No.2, pp.141-148, February 1994.
本論文の英訳公表論文:
Moritoshi Yasunaga, “Genetic Algorithms Implemented by Wafer Scale Integration ―WSI by LDA (Leaving Defects Alone) Approach ―,” Systems and Computers in Japan, SCRIPTA TECHNICA, INC., Vol.25, No.13, pp.26-36, 1994.

[7] 安永守利, “WSIを用いた自己組織化マップのフォールトトレランス,” 電子情報通信学会論文誌, Vol.J78-D-I, No.12, pp.960-971, December,1995.

[8] Moritoshi Yasunaga and Tatsuo Ochiai, “Performance Evaluation of Neural Network Hardware Using Time-Shared Bus and Integer Representation Architecture,” IEICE Transaction on Information and Systems, Vol.E79-D, No.6, pp.888-896, June 1996.

[9] Moritoshi Yasunaga, Ippei Hachiya, Keiji Moki and Jung Hwan Kim, “Fault-Tolerant Self-Organizing Map Implemented by Wafer-Scale Integration”, IEEE Transaction on VLSI Systems, Vol.6, No.2, pp.257-265, 1998.

[10] 安永守利, 八谷一平, “自己組織化マップハードウェアのフォールトトレランス評価,” 電子情報通信学会論文誌, Vol.J82-D-I, No.2, pp.410-424, February 1999.

[11] 安永守利, 高橋雅聡, 吉原郁夫, “進化的手法に基づく再構成可能な推論ハードウェア,” 情報処理学会論文誌, Vol.40, No.7, pp.3031-3042,July 1999.

[12] Moritoshi Yasunaga, Jung Hwan Kim, and Ikuo Yoshihara, “Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation,” Journal of Genetic Programming and Evolvable Machines (Kluwer Academic Publishers), Vol.2, No. 3, pp.211-230, 2001.

[13] 安永守利, 高見知親, 吉原郁夫, “FPGAを用いたナノ秒オーダ画像認識ハードウェア,” 電子情報通信学会論文誌, Vol.J84-D-II, No.10, pp.2280-2292, October, 2001.

[14] Moritoshi Yasunaga, Ikuo Yoshihara, and Jung H. Kim, “The Evolutionary Algorithm-based Reasoning System,” IEICE Transaction on Information and Systems, Vol.E84-D, No.11, pp.1508-1520, November 2001.

[15] Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, and Jung H. Kim, “The Kernel-based Pattern Recognition System Designed by Genetic Algorithms,” IEICE Transaction on Information and Systems, Vol.E84-D, No.11, pp.1528-1539, November 2001.

[16] 安永守利,吉原郁夫, “パターン認識用進化型ハードウェアシステムの開発―ソナースペクトル信号認識を対象として―,” 電子情報通信学会論文誌, Vol.J86-D-I, No.1, pp.1-13, January, 2003.

[17] 安永守利,吉原郁夫, “セグメント分割伝送線とその設計手法―VLSI実装基板のための高品質信号配線の提案―,” 電子情報通信学会論文誌, Vol.J88-D-I, No.5, pp.915-929, May, 2005.

[18] Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, and Ikuo Yoshihara, "A Reconfigurable-VLSI-based Double-lens Tracking-camera," Artificial Life and Robotics (Springer), Vol.12, No.1-2, pp.219-222, 2008.

[19] Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, and Ikuo Yoshihara, "Real-world Application on the reconfigurable-VLSI-based double-lens tracking-camera," Artificial Life and Robotics (Springer), Vol.13, No.1, pp.73-76, 2008.

[20] Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Masami Ishigro, and Ikuo Yoshihara, “A High-Signal-Integrity PCB Trace Composed of Multiple Segments for GHz VLSI Packaging: Its Prototyping and Performance Analysis,” Trans. of The Japan Institute of Electronics Packaging, Vol. 4, No.1, pp. 44-51, 2011.

[21] Moritoshi Yasunaga and Ikuo Yoshihara, "An evolutionary design methodology of printed circuit boards for high-speed VLSIs," Artificial Life and Robotics (Springer), Vol.21, No.2, pp.171-176, 2016.
DOI 10.1007/s10015-016-0266-9


2. 論文誌(査読有り)に掲載された副執筆論文(21件)

[1] Jung H. Kim, Shanuj V. Sarin, Moritoshi Yasunaga, and Hyunseo Oh, “Robust Noncoherent PN-Code Acquisition for CDMA Communication Systems, IEEE Trans. on Vehicular Technology,” Vol.50, No.1, pp.278-286, 2001.

[2] 平井有三, 落合辰男, 安永守利, “1000ニューロン100万シナプスで構成されたニューラルネットワークハードウェアシステム,” 電子情報通信学会論文誌, Vol.J84-D-II, No.6, pp.1185-1193, June 2001.

[3] 相部範之, 安永守利, “確率的ニューラルネットワーク計算の並列高速化アーキテクチャとその画像認識システムへの適用,” 情報処理学会論文誌, Vol. 43, No.SIG6(HPS5), pp.206-218, September 2002.

[4] H. D. Nguyen, I. Yoshihara, K. Yamamori, and M. Yasunaga, “Greedy Genetic Algorithms for Symmetric and Asymmetric TSPs,” 情報処理学会論文誌, Vol.43, No. SIG10(TOM7), pp.165-175, November 2002.

[5] Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “Aligning Multiple Protein Sequences by Parallel Hybrid Genetic Algorithm,” Genome Informatics (GIW2002), Genome Informatics Series No.13, pp.123-132, Universal Academic Press, 2002.

[6] Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification,” IEICE Transaction on Information and Systems, Vol. E87-D, No.7, pp.1943-1952, July 2004.

[7] Noriyuki Aibe, Ryosuke Mizuno, Masanori Nakamura, Moritoshi Yasunaga, and Ikuo Yoshihara, “Performance Evaluation System for Probabilistic Neural Network Hardware,” Artificial Life and Robotics, Vol.8, No.2, pp.208-213, Springer, 2004.

[8] Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “A Multimodal Neural Network with Single-state Predictions for Protein Secondary Structure,” Artificial Life and Robotics, Vol.8, No.2, pp.168-173, Springer, 2004.

[9] Yoshiki Yamaguchi, Moritoshi Yasunaga, Kazuya Hayashi, Noriyuki Aibe, Yorihisa Yamamoto, and Ikuo Yoshihara, "A bio-inspired tracking camera system," Artificial Life and Robotics (Springer), Vol.11, No.1 pp.128-134, 2007.

[10] Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems Nguyen, H. D. Nguyen; Yoshihara, I.; Yamamori, K.; Yasunaga M., IEEE Transactions on Systems, Man and Cybernetics, Part B, Volume 37, Issue 1, Page(s): 92 – 99, Feb. 2007.

[11] Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Moritoshi Yasunaga and Akihiko Konagaya, “Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation,” Journal of VLSI Signal Processing (Springer), Vol. 48, pp. 287-299, 2007.

[12] Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic,” IEICE Trans. Fundamentals, Vol. E90-A, No. 10, pp. 2187-2193, October, 2007.

[13] Naoki Koizumi, Kazuya Hayashi, Moritoshi Yasunaga, Kunihito Yamamori, and Ikuo Yoshihara ,"Variable-length segmental transmission line and its design guidelines," Artificial Life and Robotics (Springer), Vol.12, No.1-2, pp.214-218, 2008.

[14] Keiko Ikeda, Moritoshi Yasunaga, Yoshiki Yamaguchi, Yorihisa Yamamoto, and Ikuo Yoshihara, "A visual-inspection system using a self-organization map," Artificial Life and Robotics (Springer), Vol.14, No. 4, pp.506-510, 2009.

[15] 川合浩之, 山口佳樹,安永守利,“FPGAの動的部分再構成を利用した進化型高速パターン認識ハードウェア,” 電子情報通信学会論文誌, Vol.J93-D, No.11, pp.2354-2367, November, 2010.

[16] Masami Ishiguro, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Ikuo Yoshihara, and Moritoshi Yasunaga, "Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging," Artificial Life and Robotics (Springer), Vol.15, No. 3, pp.325-329, 2010.

[17] Masafumi Kuroda, Kunihito Yamamori, Masaharu Munemoto, Moritoshi Yasunaga, and Ikuo Yoshihara, “Development of A Novel Crossover of Hidden Genetic Algorithms for Large-scale Traveling Salesman Problems,” Artificial Life and Robotics (Springer), Vol.15, No. 4, pp.547-550, 2010.

[18] Hiroki Shimada, Shohei Akita, Masami Ishiguro, Noriyuki Aibe, Ikuo Yoshihara, and Moritoshi Yasunaga, "Digital-signal-waveform improvement on VLSI packaging including inductances," Artificial Life and Robotics (Springer), Vol.16, No. 2, pp.194-197, 2011.

[19] 伊藤則之,安永守利,“プロセッサ設計手法の現状と今後―高性能化を実現する設計フローとCADシステム―,”電子情報通信学会論文誌(サーベイ論文),Vol.J94-D, No.12, pp.2004-2030, Dec. 2011. (本論文は,第69回電子情報通信学会論文賞を受賞した.)

[20] 監物香保里,金澤健治,森 大和,相部範之,安永守利,“FPGAを用いた画像処理応用のためのMonotone Chain アルゴリズムの高速計算,”電子情報通信学会論文誌, Vol. J100-D, No.1, pp.1-13, January, 2017.

[21] Tetsuya Odaira, Naoki Yokoshima, Ikuo Yoshihara, and Moritoshi Yasunaga, "Evolutionary design of high signal integrity interconnection based on eye-diagram," Artificial Life and Robotics (Springer), Vol.23, No.3, pp.298-303, 2018.
ISSN 1433-5298, DOI 10.1007/s10015-018-0433-2
Published online: 13 April 2018.


3. 国際会議Proceedings(査読有り)に掲載された筆頭執筆論文(47件)

[1] Moritoshi Yasunaga, Minoru Yamada, Kazuo Sato, Kuninori Imai, Akira Masaki, “A Low Stray Capacitance Microconnector for High Density Packaging at Room Temperature,” Proc. of the SHM and IEEE IMC (International Microelectronics Conference), pp.108-112, 1986.

[2] Moritoshi Yasunaga, Noboru Masuda, Mitsuo Asai, Minoru Yamada, Akira Masaki, Yuzo Hirai, "A Wafer Scale Integration Neural Network Utilizing Completely Digital Circuits," Proc. of the IEEE and INNS IJCNN'89 (International Joint Conference on Neural Networks) Washington D.C., Vol.2, pp.213-217, 1989.

[3] Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Minoru Yamada, Akira Masaki, "Design, Fabrication and Evaluation of A 5-inch Wafer Scale Neural Network LSI Composed of 576 Digital Neurons," Proc. of the IEEE and INNS IJCNN'90 (International Joint Conference on Neural Networks) San Diego, Vol.2, pp.527-535, 1990.
(本論文は精選論文集:“Artificial Neural Networks ―A selected paper volume―,” IEEE press sponsored by IEEE Circuits and System Society and IEEE Neural Networks Council, 1992 に掲載された.)

[4] Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Katsunari Shibata, Mitsuo Ooyama, Minoru Yamada, Takahiro Sakaguchi, Masashi Hashimoto, “A Self-Learning Neural Network Composed of 1152 Digital Neurons in Wafer-Scale LSIs," Proc. of the IEEE and INNS IJCNN'91 (International Joint Conference on Neural Networks) Singapore, Vol.3, pp.1844-1849, 1991.

[5] Moritoshi Yasunaga and Hiroaki Kitano, “Memory-Based Reasoning implemented by Wafer Scale Integration," Proc. of the IEEE International Conference on Wafer-Scale Integration, pp.11-19, 1993.

[6] Moritoshi Yasunaga and Tasuo Ochiai, “A Digital Neural Network Hardware based on SIMD (Single Instruction Multiple Data) Architecture and Its Acceleration-Ratio Evaluation," Proc. of The 5th Int’l. Symposium on Bioelectronics and Molecular Electronic Devices,pp.257-258, 1995.

[7] Moritoshi Yasunaga, Ippei Hachiya, and Moki Keiji, “Fault-tolerance evaluation of SOM (Self-Organizing Map) using a neuro-computer:MY-NEUPOWER," Proc. of the Int’l. Conf. on Neural Information Processing (ICONIP1996), Vol.2, pp.1395-1399, 1996.

[8] Moritoshi Yasunaga and Ippei Hachiya, “SOM (Self-Organizing Map) Implemented by Wafer Scale Integration ―Its Self-Organizing Behavior under Defects ―," IEEE Int’l. Conf. on Innovative Systems in Siclicon, pp.323-329, 1996.

[9] Moritoshi Yasunaga and Yuzo Hirai, “Ising Model Calculation Using PDM Neural Network Hardware: Boltzmann Statistical Mechanics Embedded in the Hardware, " IEEE and INNS Int’l. Joint Conf. on Neural Networks, Vol.2, pp.948-952, 1997.

[10] Moritoshi Yasunaga and Masatoshi Takahashi, “A Prediction-chip and Its Evolutional Design," International Symposium on Nonlinear Theory and its Applications, Vol.2, pp.861-864, 1997 .

[11] Moritoshi Yasunaga, Akio Yamada, and Tatsuo Ochiai, “Performance of a Bus-based Parallel Computer with Integer-Representation Processors Applied to Artificial Neural Network and Parallel AI Domains," Second Int’l. Conf. on Knowledge-Based Intelligent Electronic Systems, Vol.3, pp.519-527, 1998 .

[12] Moritoshi Yasunaga and Eiji Yoshida, “Optimization of Parallel BP Implementation: Training Speed of 1,056 MCUPS on the Massively Parallel Computer CP-PACS," IEEE and INNS Int’l. Joint Conf. on Neural Networks, pp.563-568, 1998.

[13] Moritoshi Yasunaga and Masatoshi Takahashi, “Logic Design with Evolving Truth-Table (LoDETT) for Pattern Recognition LSI's," IEEE Int’l. Conf. on Evolutional Computation, pp. 318-323, 1998.

[14] Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara, “Sonar Spectrum Recognition Chip Designed by Evolutionary Algorithm," Proc. The IEEE and INNS Int’l. Joint Conf. on Neural Networks, CD-ROM, July 1999.

[15] Moritoshi Yasunaga, Eiji Yoshida, and Ikuo Yoshihara, “Parallel Back-propagation Using Genetic Algorithm: Real-time BP Learning on the Massively Parallel Computer CP-PACS,” Proc. The IEEE and INNS Int’l. Joint Conf. on Neural Networks, CD-ROM, July 1999.

[16] Moritoshi Yasunaga, Kenichi Tominaga, and Jung Hwan Kim, “Parallel Self-organization Map Using Multiple Stimuli,” Proc. The IEEE and INNS Int’l. Joint Conf. on Neural Networks, CD-ROM, July 1999.

[17] Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara, “Evolvable Sonar Spectrum Discrimination Chip Designed by Genetic Algorithm,” Proc. The IEEE Int’l. Conf. Systems, Man and Cybernetics, pp. 585-590, October 1999.

[18] Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara, “Biometrics Identification Chip and Its Design Using Evolutionary Algorithm,” International Symposium on Nonlinear Theory and its Applications, pp.235-238, Hawaii, November 1999.

[19] Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara, “A Fault-tolerant Evolvable Face Identification Chip,” Proc. Int’l. Conf. on Neural Information Processing, pp.125-130, Perth, November 1999.

[20] Moritoshi Yasunaga, Jung H. Kim, and Ikuo Yoshihara, “The Application of Genetic Algorithms to the Design of Reconfigurable Reasoning VLSI Chips, "ACM/SIGDA Proc. Int’l. Sympo. on Field Programmable Gate Arrays, pp.116-125, Monterey, February 2000.

[21] Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, and Jung H. Kim, “Genetic Algorithm-based Design Methodology for Pattern Recognition Hardware,” Proc. Int’l. Conf. on Evolvable Systems (Springer LNCS No. 1801), pp.264-273, Edinburgh, April 2000.

[22] Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, and Jung H. Kim, “Kernel Optimization in Pattern Recognition Using a Genetic Algorithm,” Proc. Genetic and Evolutionary Computation Conf., pp.391, July 2000.

[23] Moritoshi Yasunaga, Taro Nakamura, Jung H. Kim, and Ikuo Yoshihara, “Kernel-based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables,” Proc. The 2nd NASA/DoD Workshop on Evolvable Hardware, pp.253-262, July 2000.

[24] Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, and Jung H. Kim,“GA-based Kernel Optimization for Pattern Recognition: Theory for EHW Application," Proc. IEEE Congress on Evolutionary Computation, pp.545-552, July 2000.

[25] Moritoshi Yasunaga, Keiji Moki, Jung H. Kim, and Ikuo Yoshihara, “A Bus-based Neuro-computer for High Speed SOM Calculation and Its Fault Tolerance against Defective Circuits," Proc. the 6th Int’l. Conf. Soft Computing IIZUKA2000, INVITED TALK, pp.264-271, October 2000.

[26] Moritoshi Yasunaga, Ikuo Yoshihara, and Jung H. Kim, “A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI," Proc. IEEE Int’l. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000), pp.69-77, October 2000.

[27] Moritoshi Yasunaga, Noriuki Aibe, Taro Nakamura, and Ikuo Yoshihara, “DP Matching Hardware for High-speed Genome Database Machine,” Proc. Int’l. Conf. on Artificial Intelligence in Science and Technology, pp.256-261, December 2000.

[28] Moritoshi Yasunaga, Takahiro Tsuzuku, Kentaro Ushiyama, Ikuo Yoshihara, and Jugn H. Kim, "Evolvable Reasoning Hardware: Its Application to the Genome Informatics," Proc. IEEE Congress on Evolutionary Computation, pp. 704-711, May 2001.

[29] Moritoshi Yasunaga, Kentaro Ushiyama, Ikuo Yoshihara, and Jung H. Kim, “Symbolic Kernel-Based Reasoning: Its Application to the Rule Extraction in Dictyostelium discoideum DNA,” Proc. Genome Informatics 2001, Genome Informatics Series No.12, Universal Academic Press, pp.413-414, 2001.

[30] Moritoshi Yasunaga, Kentaro Ushiyama, Noriyuki Aibe, Hidetoshi Fujiwara, Ikuo Yoshihara, and Jung H. Kim, “An Evolutionary Kernel-Based Reasoning System Using Reconfigurable VLSIs: Its Hardware Prototyping and Application to the Splicing Boundary Problem,” Proc. IEEE Congress on Evolutionary Computation (The 2002 IEEE World Congress on Computational Intelligence), CD-ROM, 2002. (pp.285-290:吉原先生業績リストにはページ数記載)

[31] Moritoshi Yasunaga, Noriyuki Aibe, Ryosuke Mizuno, Masanori Nakamura, and Ikuo Yoshihara, “Power-Quake Reduction Design in VLSI,” Proc. 2002 Pacific Rim International Symposium on Dependable Computing (PRDC2002) Fast Abstract, pp.7-8, 2002.

[32] Moritoshi Yasunaga, Ikuo Yoshihara, Jung H. Kim, “Gene Finding Using Evolvable Reasoning Hardware,” Proc. Int’l. Conf. on Evolvable Systems, pp.198-207, Trondheim, Norway, 2003.

[33] Moritoshi Yasunaga, Ikuo Yoshihara, and Jung, H. Kim, “The Design of Segmental-Transmission-Line for High-Speed Digital Signals Using Genetic Algorithms,” Proc. IEEE Congress on Evolutionary Computation (CEC) 2003, Vol. 3. pp.1748-1755, Canberra, Australia, 2003.

[34] Moritoshi Yasunaga, Kentaro Ushiyama, Ikuo Yoshihara, Daekwan Seo, and Jung H. Kim, “An Application of The Spotting Technique to Detect Transcription-Regulatory-Elements In DNA Sequances,” Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[35] Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, and Ikuo Yoshihara, “A Reconfigurable-VLSI-based Double-lens Tracking-camera,” Proc. The 12th Int’l Symp. on Artificial Life and Robotics 2007 (AROB 12th’07), CD-ROM (4 pages), Ooita, Japan, January 2007.

[36] Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, and Ikuo Yoshihara, “Real-world Applications on the Reconfigurable-VLSI-based Double-lens Tracking-camera,” Proc. The 13th Int’l Symp. on Artificial Life and Robotics 2008 (AROB 13th’08), pp.873-876, Ooita, Japan, January 2008.

[37] Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, and Jung H. Kim, “The Segmental-Transmission-Line: Its Design and Prototype Evaluation,” Proc. The 8th International Conference on Evolvable Systems (Springer, Lecture Notes in Computer Science 5216, G. S. Hornby, L. Sekanina, P. C. Haddow Eds.), pp.130-140 Prague, Czech Republic, Sept. 2008.
(本論文は,本会議における最優秀論文賞を受賞した.)

[38] Moritoshi Yasunaga, Hiroshi Nakayama, Youki Shimauchi, Noriyuki Aibe, Yoshiki Yamaguchi, and Ikuo Yoshihara, “Prototyping of A Novel PCB-Trace Composed of Multiple Segments and Its Signal-Integrity Evaluation,” Proc. of IEEE The 11th International Conf. on Electronics, Materials and Packaging 2009 (EMAP 2009), CD-ROM (EM09-13-02), Malaysia, Dec. 2009.

[39] Moritoshi Yasunaga, Hiroshi Nakayama, Yuki Shimauchi, and Ikuo Yoshihara, “Digital-Signal-Waveform Improvement for High-Speed VLSI Packaging,” Proc. of International Symposium on Nonlinear Theory and its Applications 2010 (NOLTA2010), pp. 269-272, Poland, Sep. 2010.

[40] Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Masami Ishiguro, and Ikuo Yoshihara, “A High Signal-Integrity PCB-Trace Composed of Multiple Segments for VLSI Packaging in GHz Domain, Proc. of IEEE International Conference on Electrical Packaging 2011 (ICEP2011), pp. 766-771, Nara Japan, April, 2011.

[41] Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, and Ikuo Yoshihara, “High Signal and Power Integrity Design for VLSI Packaging Using Genetic Algorithms,” Proc. The 17th Int’l Symp. on Artificial Life and Robotics 2012 (AROB 17th’12), pp.146-149, Ooita, Japan, January 2012.

[42] Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, and Ikuo Yoshihara, “Segmental Transmission Line: Its Practical Application -The Optimized PCB Trace Design Using a Genetic Algorithm-,” Proc. The IEEE Symposium Series on Computational Intelligence 2014/ International Conference on Evolvable Systems 2014, pp.23-30, Orlando, Florida, U.S.A., December 2014.

[43] Moritoshi Yasunaga, and Ikuo Yoshihara, “An Evolutionary Design Methodology of Printed Circuit Boards for High-speed VLSIs,” Proc. The 20th Int’l Symp. on Artificial Life and Robotics 2015 (AROB 20th’15), pp.498-501, Ooita, Japan, January 2015.

[44] Moritoshi Yasunaga, Ikuo Yoshihara, “Bio-inspired Design of High-speed Transmission Line -High Signal Integrity Design for Printed Circuit Board Traces in GHz Domain-,” Proc. the Fourth International Conference on Intelligent Systems and Applications (INTELLI )2015, pp. 23-25, St Julian’s, Malta, Oct. 2015.

[45] Moritoshi Yasunaga, Yusuke Kuribara, Hirofumi Inoue, Ikuo Yoshihara, “Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines -Towards Realization of Branched Traces for High-Speed Data Transfer in PCBs -,” Proc. The IEEE Symposium Series on Computational Intelligence 2015/ International Conference on Evolvable Systems 2015, pp.1236-1243, Captownn, South Africa, December 2015.

[46] Moritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara, “A Passive Equalizer and Its Design Methodology for Global Interconnects in VLSIs,” Proc. 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2016), 6 pages in USB memory, Tallin, Estonia, September, 2016.

[47] Moritoshi Yasunaga and Ikuo Yoshihara, “Waveform Learning Based on a Genetic Alogorithm and Its Application to Signal Integrity Improvement,” Prof. 2017 4th IEEE International Conference on Soft Computing and Machine Intelligence (ISCMI 2017), pp. 145-148, Republic of Mauritius, Nov. 23-24, 2017.
DOI: 10.1109/ISCMI.2017.8279615


4. 国際会議Proceedings(査読有り)に掲載された副執筆論文(83件)

[1] M.Yamada, M.Yasunaga, N.Masuda, M.Yagyu, M.Asai, K.Shibata, M.Ooyama, T.Sakaguchi and M.Hashimoto, “A Neural Network on Wafer Scale Integration," Proceedings of the IEEE International Conference on Wafer-Scale Integration, pp.231- , 1992.

[2] Hiroaki Kitano and Moritoshi Yasunaga, “Wafer Scale Integration for Massively Parallel Memory-Based Reasoning,” Proceedings of the Tenth National Conference on Artificial Intelligence (AAAI'92), pp.850 - 856, 1992.

[3] Yuzo Hirai and Moritoshi Yasunaga, “A PDM Digital Neural Network System with 1,000 Neurons Fully Inteconnected Via 1,000,000 6-Bit Synapses," Proc. of the Int’l. Conf. on Neural Information Processing, Vol.2, pp.1251-1256, 1996.

[4] Ikuo Yoshihara,Tomoyuki Nakagawa and Moritoshi Yasunaga, “A multi-modal neural network using Chebyschev Polynomials,” Proc. 13th Korea Automatic Control Conference, pp.250-253, October 1998.

[5] H.Koizumi,T.Ochiai,T.Okahashi,Y.Yamashita,A.Maki,T.Yamamoto,Y.Inagami,
H.Yoshizaw,M.Iwata,T.Ohmori,M.Yasunaga, “Dynamic Optical Topography and the Real-time PDP chip: An Analytical and Synthetical Approach to High-order Brain Function,” 5th Int’l. Conf. Neural Information Processing, pp. 337-340, Octorber 1998.

[6] Ikuo Yoshihara, Tomoyuki Nakagawa, Moritoshi Yasunaga, and Ken-ichi Abe, “A multi-modal Neural Network using Chebyschev Polynomials and its Application,” Proc. The IEEE and INNS Intl. Joint Conf. on Neural Networks, CD-ROM, July 1999.

[7] Ikuo Yoshihara, Masaaki Inaba, Tomoo Aoyama, and Moritoshi Yasunaga, “A Construction Method of Multiple Control Systems Using Partial Knowledge Upon System Dynamics,” Proc. 14th Korea Automatic Control Conference, pp.E73-E78, October 1999.

[8] I. Yoshihara, M. Numata, T. Aoyama, M. Yasunaga, and K. Abe, “Extending Prediction Term of GP-Based Time Series Model,” Proc. the 5-th Int. Symp. on Artificial Life and Robotics, pp.268-271, Ohita, 2000.

[9] Ikuo Yoshihara, Tomoo Aoyama, and Moritoshi Yasunaga, “A Fast Model-Building Method for Time Series Using Genetic Programing,” Proc. Genetic and Evolutionary Computation Conf., pp.537, July 2000.

[10] Ikuo Yoshihara, Tomoo Aoyama, and Moritoshi Yasunaga, “GP-Based Modeling Method for Time Series Prediction with Parameter Optimization and Node Alternation,” Proc. IEEE Congress on Evolutionary Computation, pp.1475-1481, July 2000.

[11] Hiroshi Yano, Ikuo Yoshiyara, Tomoo Aoyama, and Moritoshi Yasunaga, “An Application of GP-based Prediction Model to Sunspots,” Proc.15th Korea Automatic Control Conference, pp.FPI18-3 CD-ROM, October 2000.

[12] Ikuo Yoshiyara, Tomoo Aoyama, and Moritoshi Yasunaga, “Financial Application of Time Series Prediction based on Genetic Programming,” Proc.15th Korea Automatic Control Conference, pp.FPI18-4, October 2000.

[13] H.D.Nguyen, Ikuo Yoshihara, and Moritoshi Yasunaga, “Modified Edge Recombination Operators of Genetic Algorithms for the Traveling Salesman Problem,” Proc. IEEE Int. Conf. on Industrial Electronics, Control, and Instrumentation (SEAL session), pp.2815-2820, October 2000.

[14] H. D. Nguyen, I. Yoshihara, T. Aoyama, M. Yasunaga, “Directed Edge Recombination Operator of Genetic Algorithms for Asymmetric Traveling Salesman Problems,” Proc. Int. Conf. on Artificial Intelligence in Science and Technology, pp.56-61, December 2000.

[15] Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara, “Self-learning Probabilistic Neural Network Hardware Using Reconfigurable LSIs,” Proc. Int. Symposium on Artificial Life and Robotics 2001, pp.89-92, January 2001.

[16] Noriyuki Aibe, Moritoshi Yasunaga, and Ikuo Yoshihara, “Probabilistic Neural Network Processor for Image Recognition Using Reconfigurable LSIs, “ Proc. 2001 Int’l Symposium on Nonlinear Theory and Its Application (NOLTA2001), Vol.1, pp.111-114, 2001.

[17] I. Yoshihara, Y. Kamimai, K. Yamamori, and M. Yasunaga, “A Multi-modal Neural Network for Identifying Exon-Intron Boundaries,” Baba, N., Jain, L.C., and Howlett, R.J. (Eds), Knowledge-based Intelligent Information Engineering Systems and Allied Technologies, IOS Press, Holland, pp.998-1002, 2001.

[18] Ikuo Yoshihara and Moritoshi Yasunaga, “Generating Complicated Models for Time Series Using Genetic Programming, Proc. Int’l Conf. Control, Automation and Systems (ICCAS) 2001, pp.955-958, 2001.

[19] Ikuo Yoshihara, Yoshiyuki Kamimai, and Moritoshi Yasunaga, “Feature Extraction from Genome Sequence Using Multi-Modal Neural Networks,” Proc. Genome Informatics 2001, Genome Informatics Series No.12, Universal Academic Press, pp.420-422, 2001.

[20] H. D. Nguyen, I. Yoshihara, K. Yamamori, and M. Yasunaga, “Parallel Hybrid Genetic Algorithm for Multiple Protein Sequence Alignment,” Proc. IEEE Congress on Evolutionary Computation (The 2002 IEEE World Congress on Computational Intelligence), CD-ROM, 2002.

[21] Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara, and Jung, H. Kim, “A Probabilistic Neural Network Hardware System Using A Learning-Parameter Parallel Architecture, Proc. IEEE Int’l Joint Conf. on Neural Networks (The 2002 IEEE World Congress on Computational Intelligence), CD-ROM, 2002. (pp.2270-2275:吉原先生業績リストにはページ数記載)

[22] Hanxi Zhu, Kunihito, Ikuo Yoshihara, Yamamori, and Moritoshi Yasunaga, “Prediction of Protein Secondary Structure by Multi-modal Neural Network, Proc. 4th Asia-Pacific Conference on Simulated Evolution And Learning 2002 ( SEAL’02), CD-ROM, 2002.

[23] Takehiro Ohta, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “GP-based Method for Identifying Exon Region in DNA Sequences, “Proc. 4th Asia-Pacific Conference on Simulated Evolution And Learning 2002 ( SEAL’02), CD-ROM, 2002.

[24] N. Aibe, R. Mizuno, M. Nakamura, M. Yasunaga, and I Yoshihara, “Performance Evaluation System for Probabilistic Neural Network Hardware,” Proc. Int’l. Symposium on Artificial Life and Robotics 2003, pp.471-474, January 2003.

[25] ] H. Zhu, I. Yoshihara, K. Yamamori, and M. Yasunaga, “A Multi-modal Neural Network with Single -state Predictions for Protein Secondary Structure,” Proc. Int’l. Symposium on Artificial Life and Robotics 2003, pp.475-478, January 2003.

[26] Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “Improved GA-based Method for Multiple Protein Sequence Alignment,” Proc. IEEE Congress on Evolutionary Computation (CEC) 2003, Vol. 3. pp.1826-1832, Canberra, Australia, 2003.

[27] Noriuki Aibe and Moritoshi Yasunaga, “Reconfigurable Parallel Comparation Architecture and Its Application to IP Packet Filters,” Proc. IEEE Int’l Conf. Field-Programmable Technology (ICFPT) 2003, pp.363-366, Tokyo, December, 2003.

[28] Ryosuke Mizuno, Noriuki Aibe, Moritoshi Yasunaga, and Ikuo Yoshihara, “Reconfigurable Architecture for Probabilistic Neural Network System, ” Proc. IEEE Int’l Conf. Field-Programmable Technology (ICFPT) 2003, pp.367-370, Tokyo, December, 2003.

[29] Daekwan Seo, Moritoshi Yasunaga, and Jung H. Kim, “A Computational Approach to Detect Transcription Regulatory Elements in Dictyostelium Discoideum,” Proc. IEEE Congress on Evolutionary Computation (CEC) 2004, Portland, 2004.

[30] Noriyuki Aibe, Moritoshi Yasunaga, "Meta-I/O Interface Using Reconfigurable LSIs", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2004), Hiroshima, Japan, 25-28 July 2004.

[31] Masakazu Sato, Ikuo Yoshihara, H. D. Nguyen, Kunihito Yamamori, and Moritoshi Yasunaga, “Hybrid GA Using Edge Assembly Crossover and Lin-Kernighan Heuristic,” Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[32] Yusuke Higashi, Ikuo Yoshihara, Hanxi Zhu, “English Pronunciation Reasoning Considering Frequency on Appearance of Phonemes by Neural Network,” Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[33] Toshiro Onitani, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “Extraction of Feature Patterns Embedded in Non-Transcribed Region of Dictyostelium Discoideum,” Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[34] Yoshiyuki Sakaguchi, Ikuo Yoshihara, Naoki Koizumi, Kunihito Yamamori, and Moritoshi Yasunaga, “GA-based Timetabling for Satisfying Professors’ and Students’ Requirements,” Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[35] Kouji Ohta, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “GMDH-based Model Optimized by GA for Extracting EXON Regions From DNA Sequences,” Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[36] Hung Dinh, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “A Parallel Hybrid Genetic Algorithm for Large Scale TSPs, “Proc. The 5th Int’l Conf. Simulated Evolution And Learning, CD-ROM, Busan, 2004.

[37] Noriyuki Aibe and Moritoshi Yasunaga, “Reconfigurable I/O Interface for Mobile Equipments,” Proc. Int’l Conf. Field-Programmable Technology, pp. 359-362, Brisbane, 2004.

[38] Daekwan Seo, M. Yasunaga, I.S. Kim, B.W. Ham, and Jung H. Kim, “Finding Transcriptional Regulatory Elements in Dictyostelium Gene Expression,” Proc. IEEE Congress on Evolutionary Computation (CEC) 2005, CD-ROM, Edinburgh, England, 2005.

[39] Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, and Moritoshi Yasunaga, “Variable Length Segmental-Transmission-Line and Its Parameter Optimization based on GA,” Proc. IEEE Congress on Evolutionary Computation (CEC) 2005, CD-ROM, Edinburgh, England, 2005.

[40] Kazuya Hayashi, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Moritoshi Yasunaga, and Ikuo Yoshihara, ''A Bio-inspired Tracking-camera System'', International Symposium on Artificial Life and Robotics (AROB 11th '06), pp.755-758, Oita, Japan, January 2006.

[41] Hiroyuki Kawai, Yoshiki Yamaguchi, and Moritoshi Yasunaga, ''Improvement of module redundancy using FPGA'', 6th European Workshop on Microelectronics Education (EWME2006), pp.67-70, Stockholm, Sweden, June 2006.

[42] Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, and Yoshiki Yamaguchi, ''On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition'', First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), pp.373-380, IEEE Computer Society, Istanbul, Turkey, June, 2006.

[43] Koizumi, N., Yoshihara, I., Yamamori, K., and Yasunaga,M.:"Enhancement of the Variable-Length- Transmission-Line design method for multi-point optimization", Proc. 2006 IEEE Congress on Evolutionary Computation (CEC2006), CD-ROM, Vancouver, 2006.

[44] Nguyen D.H., Yoshihara, I., Yamamori, K. and Yasunaga, M."A New Three-Level Tree Data Structure for Optimizing the Traveling Salesman Problem by Lin-Kernighan Heuristic",2006 International Symposium on Nonlinear Theory and its Applications(NOLTA2006), 2006, 871-874, Bologna, 2006.

[45] Hiroyuki Kawai, Yoshiki Yamaguchi, and Moritoshi Yasunaga, ''Realization of the sound space environment for the radiation-tolerant space craft'', the 3rd International Conference on ReConFigurable Computing and FPGAs (ReConFig2006), pp.198-205, San Luis Potosi, Mexico, September 2006.

[46] N.Koizumi, K.Hayashi, M.Yasunaga, K.Yamamori, and I.Yoshihara, “Variable-Length-Segmental-Transmission-Line and its Design Guidelines,” Proc. The 12th Int’l Symp. on Artificial Life and Robotics 2007 (AROB 12th’07), CD-ROM (4 pages), Ooita, Japan, January 2007.

[47] K. Glette, J. Torresen, and M. Yasunaga. An Online EHW Pattern Recognition System Applied to Face Image Recognition. In Applications of Evolutionary Computing, EvoWorkshops2007: EvoCOMNET, EvoFIN, EvoIASP, EvoInteraction, EvoMUSART, EvoSTOC, Evo-TransLog, volume 4448 of Lecture Notes in Computer Science, pages 271–280. Springer-Verlag, 2007.

[48] K. Glette, J. Torresen, and M. Yasunaga, “Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA,” Proceedings of the 2007 NASA /ESA Conference on Adaptive Hardware and Systems(AHS 2007), Edinburgh, UK, p.p. 463-470, IEEE Computer Society, 2007.

[49] K. Glette, J. Torresen, and M. Yasunaga,” An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification,” Proc. Seventh International Conference, ICES 2007, volume 4684 of Lecture Notes in Computer Science, p.p. 1-12. Springer-Verlag,2007.

[50] Yusuke Arai, Ryo Sawai, Yoshiki Yamaguchi, Tsutomu Maruyama, and Moritoshi Yasunaga, ''A Lattice Gas Cellular Automata Simulator with Cell Broadband Engine'', Parallel Computing 2007 (ParCo2007), pp.459-466, Jülich, Germany, September 2007.

[51] Yoshiki Yamaguchi, Noriyuki Aibe, Moritoshi Yasunaga, Yorihisa Yamamoto, Takaaki Awano, and Ikuo Yoshihara, “Bio-Inspired Functional Asymmetry Camera System,” Proc. of the Int’l. Conf. on Neural Information Processing (ICONIP2007), pp.637–646, Kitakyusyu, Japan, November 2007.

[52] Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette and Jim Torresen, “A Self-Adaptive Pattern Recognition Hardware with On-chip Partial Reconfiguration,” Proc. International Conference on Field-Programmable Technology 2008 (ICFPT'08), pp.169-176 Taipei, Taiwan, December 2008.

[53] Keiko Ikeda, Moritoshi Yasunaga, Yoshiki Yamaguchi, Yorihisa Yamamoto, Ikuo Yoshihara, “A Visual-inspection System Using Self-organizing Map”, Proc. International Symposium on Artificial Life and Robotics 2009 (AROB 14th '09), pp.654-657, Ooita, Japan, February 2009.

[54] Yusuke Arai, Yoshiki Yamaguchi, Tsutomu Maruyama, and Moritoshi Yasunaga, “Experience of Lattice Gas Automata Simulator -- toward large-scale PlayStation 3 cluster –”, Proc. Parallel and Distributed Computing and Networks 2009 (PDCN2009), pp.181-188, Innsbruck, Austria, February 2009.

[55] Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga,“Tile-Based Fault-Tolerant Approach using Partial Reconfiguration”, International Workshop on Applied Reconfigurable Computing, pp.293-299, Karlsruhe, Germany, March 2009.

[56] Yuka Koyama, Kentaro Nishimuta, Kunihito Yamamori, Moritoshi Yasunaga, and Ikuo Yoshihara, “Quest for Genetic Information Hidden behind Disorder in DNA Sequences,” Proc. International Symposium on Artificial Life and Robotics 2010 (AROB 15th '10), pp.824-827, Ooita, Japan, February 2010.

[57] Masafumi Kuroda, Kunihito Yamamori, Masaharu Munemoto, Moritoshi Yasunaga, and Ikuo Yoshihara, “Development of A Novel Crossover of Hidden Genetic Algorithms for Large-scale Traveling Salesman Problems,” Proc. International Symposium on Artificial Life and Robotics 2010 (AROB 15th '10), pp.828-831, Ooita, Japan, February 2010.

[58] Masami Ishiguro, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Yoshiki Yamaguchi, Ikuo Yoshihara, and Moritoshi Yasunaga, “Signal Integrity Improvement Method and Its Robustness Evaluation for VLSI and VLSI-packaging,” Proc. International Symposium on Artificial Life and Robotics 2010 (AROB 15th '10), pp.832-835, Ooita, Japan, February 2010.

[59] Masafumi Kuroda, Kunihito Yamamori, Masaharu Munetomo, Moritoshi Yasunaga, and Ikuo Yoshihara, “A Proposal for Zoning Crossover of Hybrid Genetic Algorithms for Large-scale Traveling Salesman Problems,” Proc. IEEE WCCI (World Congress on Computational Intelligence) 2010, pp. 646-651, July, 18-23, Barcelona, Spain, 2010.

[60] Masami Ishiguro, Hiroki Shimada, Shohei Akita, Ikuo Yoshihara, and Moritoshi Yasunaga, “Novel Design-Methodology for PCB Traces Ensuring High Signal-Integrity on Random Signals,” Proc. The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies 2010 (SASIMI ’10), pp.70-75, Oct. Taipei, 2010.

[61] Katsuhiko Harazaki and Moritoshi Yasuanga, “Systematic Yield Optimization for Restricted PPC Pattern Generation with Genetic Algorithm,” Proc. The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies 2010 (SASIMI ’10), pp. 314-319, Oct. Taipei, 2010.

[62] Hiroki Shimada, Shohei Akita, Masami Ishiguro, Noriyuki Aibe, Ikuo Yoshihara, and Moritoshi Yasunaga, “Digital-signal-waveform improvement on VLSI packaging including inductances,” Proc. International Symposium on Artificial Life and Robotics 2011 (AROB 16th '11), pp. 375-378, Ooita, Japan, February 2011.

[63] Shohei Akita, Hiroki Shimada, Masami Ishiguro, Noriyuki Aibe, Ikuo Yoshihara, and Moritoshi Yasunaga “Digital-signal improvement-method using Pareto optimization,” Proc. International Symposium on Artificial Life and Robotics 2011 (AROB 16th '11), pp. 379-382, Ooita, Japan, February 2011.

[64] Hiroki Shimada, Shohei Akita, Masami Ishiguro, Moritoshi Yasunaga, and Ikuo Yoshihara, “Signal-Integrity improvement based on the Segmental Transmission-Line,” IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS 2011), pp.251-254, October 23-26, San Jose, California, 2011.

[65] Hiroki Shimada, Shohei Akita, Yusuke Kuribara, Ikuo Yoshihara, and Moritoshi Yasunaga,“Signal Integrity Improvement in Lossy Transmission Line Using Segmental Transmission Line,” IEEE Proc. Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) 2012, December 10-11, 2012, Taipei,Taiwan.

[66] Katsuyuki Seki, Hiroki Shimada, Ikuo Yoshihara Moritoshi Yasunaga,“Crosstalk-noise Reduction Using Segmental Transmission Line,” IEEE Proc. Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) 2012, December 10-11, 2012, Taipei,Taiwan.

[67] Katsuyuki Seki, Kenji Kanazawa, and Moritoshi Yasunaga, “Crosstalk-noise Reduction in GHz Domain Using Segmental Transmission Line,” Proceedings of 2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2013), pp. 96-99, Nara, Japan, Dec. 2013.

[68] Hidefumi Inoue, Moritoshi Yasunaga, Kenji kanazawa, and Noriyuki Aibe, “Signal Integrity Evaluation of Segmental Transmission Line under Real-world Application, “ Proceedings of 2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2013), pp. 108-111, Nara, Japan, Dec. 2013.

[69] Kazuma Shibasaka, Kenji Kanazawa, and Moritoshi Yasunaga, “Decoupling-capacitor Allocation Problem Solved by Genetic Algorithm,” Proceedings of 2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2013), pp. 225-228, Nara, Japan, Dec. 2013.

[70] Norio Chujyo, Yutaka Uematsu, and Moritoshi Yasunaga, “Power Efficient Data Rate for Photonic Interposer,” Proceeding of IEEE CPMT Symposium Japan 2014 (ICSJ2014), pp. 23-26, Kyoto, Japan, Nov. 2014.

[71] Norio Cujo, Gou Shinkai, Yasunobu Matsuoka, Hiroki Yamashita, and Moritoshi Yasunaga, “Crosstalk Reduction for Compact Optical Transceiver Module,” Proceedings of 2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2014), CD-ROM 4 pages, , Bangalore, India, Dec. 2014.

[72] Kenji Kanazawa, Kahori Kemmotsu, Yamato Mori, Noriyuki Aibe, and Moritoshi Yasunaga, “High-Speed Calculation of Convex Hull in 2D Images Using FPGA,” Symposyum on Parallel Computing with FPGAs 2015, pp.533-542, 2015.

[73] Syun Akutsu, Ikuo Yoshihara, and Moritoshi Yasunaga, “An Evolutionary Design Methodology for High Speed Point-to-Point Transmission Line Used in Printed Circuit Boards,” Proc. International Symposium on Artificial Life and Robotics 2016 (AROB 21th '16), pp. 317-321, Ooita, Japan, January 2016.

[74] Shohei Sassa, Kenji Kanazawa, Shaowei Cai and Moritoshi Yasunaga, “An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search,” ACM SIGARCH Computer Architecture News 44(4), pp.33-37 (Post Proceedings of 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), Hong Kong, July, 2016.

[75] Naoki Yokoshima and Moritoshi Yasunaga, “Signal Integrity Improvement Design of Lossy Transmission Line Based on a Single-shot Pulse,” Proceedings of 2016 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2016), pp.149-151, Hawaii, U.S.A, December 2016.

[76] Shumpei Matsuoka and Moritoshi Yasunaga, “A High Signal Integrity Interconnect Design Using a Genetic Algorithm and Its Solution Analysis,” Proceedings of 2016 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2016), pp.185-187, Hawaii, U.S.A, December 2016.

[77] Tetsuya Odaira, Naoki Yokoshima, Ikuo Yoshihara, and Moritoshi Yasunaga, “Evolutionary Design of High Signal Integrity Interconnection Based on Eye-diagram,” Proc. International Symposium on Artificial Life and Robotics 2017 (AROB 22th '17), pp. 535-540, Ooita, Japan, January 2017.

[78] Shunpei Matsuoka, Shun Akutsu, and Moritoshi Yasunaga, “High Signal Integrity Design for Transmission System Including High-Parasitic Inductance Connectors, “ Proc. IEEE CPMT Symposium Japan 2017, pp. 133-134, Kyoto Japan, Nov. 20-22, 2017.

[79] Takumu Shimada, Hiroto Komatsu, Yuuki Kawahara, Noriyuki Utagawa, Chitose Kuroda, Ikuo Yoshihara, and Moritoshi Yasunaga, “An impact-echo method using self-organizing map,” Proc. International Symposium on Artificial Life and Robotics 2018 (AROB 22th '18), pp. 490-493, Ooita, Japan, January 2018.

[80] Hiroto Komatsu, Takumu Shimada, Yuuki Kawahara, Noriyuki Utagawa, Chitose Kuroda, Ikuo Yoshihara, and Moritoshi Yasunaga, “Hardware implementation of a self-organizing map using a zynq FPGA and its application to impact-echo testing,” Proc. International Symposium on Artificial Life and Robotics 2018 (AROB 22th '18), pp. 494-497, Ooita, Japan, January 2018.

[81] Shunpei Matsuoka and Moritoshi Yasunaga, “High Signal Integrity Transmission Line Using Microchip Capacitors and its Design Methodology, “ Proc. 7th Electronic System-Integration Technology Conference (ESTC) 2018, 4 pages, Dresden Germany, Sept. 18-21, 2018.

[82] Yuya Hoshino, Shumpei Matsuoka, Tetsuya Odaira, Takashi Matsumoto, Ikuo Yoshihara,and Moritoshi Yasunaga, “Evolutionary design methodology for waveform shaping in GHz transmission line,” Proc. International Symposium on Artificial Life and Robotics 2019 (AROB 22th '19), pp. 711-714, Ooita, Japan, January 2019.

[83] Yuuki Kawahara, Hiroto Komatsu, Takumu Shimada, Noriyuki Utagawa, Chitose Kuroda, Ikuo Yoshihara, and Moritoshi Yasunaga, “Design and performance evaluation of a self-organizing map implemented on a Zynq FPGA,” Proc. International Symposium on Artificial Life and Robotics 2019 (AROB 22th '19), pp. 715-718, Ooita, Japan, January 2019.